PWRU Circuit

Power Distribution

The main components of the Power Unit are the PSA ( Power Supply Asic) and the CHAPS ( Charger Power Switch ).

In normal operation the baseband is powered from the phone's battery. The battery consists of three Nickel Metal Hydride cells. There is also a possibility to use batteries consisting of one Lithium-Ion cell. An external charger is used for recharging the battery and supplying power to the phone. The charger can be either a standard charger that can deliver around 400 mA or a so called performance charger, which can deliver supply current up to 850 mA.

The baseband contains components that control the power distribution to the whole phone excluding those parts that use continuous battery supply. The battery feeds power directly to three parts of the system: PSA, RF-power amplifier, and UI (buzzer and display and keyboard lights).

The power management circuit CHAPS provides protection against overvoltages, charger failures and pirate chargers etc. that could otherwise cause damage to the phone.

Table 2. DC Characteristics of PWRU signals

Signal name

From To

Parameter

Minimum

Typical

Maximum

Unit

Function

VBATT

Battery RF/UIF

Voltage

3.0

3.6

5.0/5.3

V

Supply voltage for RF and UIF

Current

3500

mA

XRES

MCU,NAS-TA,UIF

Logic high "1"

0.7*VL

VL

V

PSA is Power On Mode

Logic low "0"

0

0.3*VL

V

PSA is Power Off or Reset Mode

Technical Documentation Baseband Module JP3

Table 2. DC Characteristics of PWRU signals (continued)

Signal name

From To

Parameter

Minimum

Typical

Maximum

Unit

Function

LIM

MCU CHAPS

Logic high "1"

VL-0.5

VL

V

Cutoff limit 5.0 V

Logic low "0"

0

0.4

V

Cutoff limit 4.6 V

XPWRON

UIF PSA

Logic high "1"

0.7* VBAT

VBAT

V

Power On switch open

Logic low "0"

0

1.2

V

Power On switch closed

XPWR OFF

MCU PSA

Logic high "1"

VL-0.5

VL

V

Watchdog counter not reset

Logic low "0"

0

0.4

V

Watchdog counter reset "1" -> "0"

PWRON

PSA MCU

Logic high "1"

0.7*VL

VL

V

PSA is in Power On Mode

Logic low "0"

0

0.3*VL

V

PSA is in Power Off or Reset mode

PSBS_EN

(Phone Supported Battery Save)

NASTA PSA

Logic high "1"

2.0

2.90

V

VRX Enabled

Logic low "0"

0

0.5

V

VRX Disabled

HPD_EN

NASTA PLL circuit

Logic high "1"

2.0

2.90

V

Harware power down disabled on PLL circuit

Logic low "0"

0

0.4

V

Hardware power down enabled on PLL circuit

VTX_ENA

MCU PSA

Logic high "1"

VL-0.5

VL

V

TX VCO and synthesizer powered on

Logic low "0"

0

0.4

V

TX VCO and synthesizer powered off

VBATSW

PSA MCU

Voltage

0

2.45

V

Switched internally di-vited VBAT voltage

VBATSW/VBAT division ratio

0.436

0.45

0.464

VCHARG

PSA MCU

Voltage

0

2.8

V

Switched Charger voltage

VCHRSW switch resistance

0

0.25

1.0

Kohm

MCU

Voltage

0

2.90

V

Charger Current Measurement over the shunt resistor.

TXD

MCU PSA

Logic high "1"

VL-0.5

VL

V

M2BUS data output, PSA M2BUS output is in high-Z state.

Logic low "0"

0

0.4

V

M2BUS data output, PSA M2BUS output is LOW

Baseband Module JP3 Technical Documentation

Table 2. DC Characteristics of PWRU signals (continued)

Signal name

From To

Parameter

Minimum

Typical

Maximum

Unit

Function

RXD

PSA MCU

Logic high "1"

2.0

2.90

V

M2BUS data input

Logic low "0"

0

0.5

V

CSW

MCU PSA

Logic high "1"

2.0

2.90

V

Charger switch and ACP-9 control signal

Logic low "0"

0

0.5

V

PWM frequency

1

32

Hz

PWM duty cycle

0

100

Acceptable chargers are detected by the software. The absolute maximum input voltage is 30V due to the transient suppressor that is protecting the charger input. At the phone end there is no difference between a plug-in charger or a desktop charger. The DC-jack pins and bottom connector charging pads are connected together inside the phone. The charging block diagram is below.

MCU «

LIM

CHAPS

VOUT

RSENSE VCH

PWM

GND

±

10k

50.3k

TRANSCEIVER

50.3k

CHRG CTRL

L GND

CHARGER

NOT IN ACP-7

Figure 2. Charging block diagram

Startup charging

When a charger is connected, the CHAPS is supplying a startup current minimum of 130mA to the phone. The startup current provides initial

Technical Documentation Baseband Module JP3

charging to a phone with an empty battery. The startup circuit charges the battery until the battery voltage level reaches 3.0V (+/- 0.1V) and the PSA releases the PURX reset signal and program execution starts. Charging mode is changed from startup charging to PWM charging that is controlled by the MCU software. If the battery voltage reaches 3.55V (3.75V maximum) before the program has taken control over the charging, the startup current is switched off. The startup current is switched on again when the battery voltage has decreased to 100mV (nominal).

Table 3. Startup characteristics

Parameter

Symbol

Min

Typ

Max

Unit

VOUT Start- up mode cutoff limit

Vstart

3.45

3.55

3.75

V

VOUT Start- up mode hysteresis NOTE: Cout = 4.7 uF

Vstarthys

80

100

200

mV

Start-up regulator output current VOUT = 0 V ... Vstart

Istart

130

165

200

mA

Battery overvoltage protection

Output overvoltage protection is used to protect phone from damage. This function is also used to define the protection cutoff voltage for different battery types (Li or Ni). The power switch is immediately turned OFF if the voltage in VOUT rises above the selected limit VLIM1 or VLIM2.

Table 4. VLIM characteristics

Parameter

Symbol

LIM input

Min

Typ

Max

Unit

Output voltage cutoff limit (during transmission or Li-battery)

VLIM1

LOW

4.4

4.6

4.8

V

Output voltage cutoff limit (no transmission or Ni-battery)

VLIM2

HIGH

4.8

5.0

5.2

V

The voltage limit (VLIM1 or VLIM2) is selected by logic LOW or logic HIGH on the CHAPS (N101) LIM- input pin. Default value is lower limit VLIM1.

When the switch in output overvoltage situation has once turned OFF, it stays OFF until the the battery voltage falls below VLIM1 (or VLIM2) and PWM = LOW is detected. The switch can be turned on again by setting PWM = HIGH.

Baseband Module JP3

Technical Documentation

"VCHl I

I VCH<VOUT

VOUT A

I VLIM1 or VLIM2

SWITCH

Figure above: Battery overvoltage protection

Battery removal during charging

Output overvoltage protection is also needed in case the main battery is removed when a charger connected or a charger is connected before the battery is connected to the phone.

With a charger connected, if VOUT exceeds VLIM1 (or VLIM2), the CHAPS turns switch OFF until the charger input has decreased below Vpor (nominal 3.0V, maximum 3.4V). The MCU software stops the charging (turn off PWM) when it detects that the battery has been removed. The CHAPS remains in protection state as long as the PWM stays HIGH after the output overvoltage situation has occurred.

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Baseband Module JP3

VCH Vpor

(Standard

Charger)

VCH Vpor

(Standard

Charger)

Istart off due to VCH<Vpor

VOUT

VLIM

4V Vstart

SWITCH

Droop depends on load & C in phone

Droop depends on load & C in phone

VLIM

4V Vstart

Istart off due to VCH<Vpor

1. Battery removed, (standard) charger connected, VOUT rises (follows charger voltage)

2. VOUT exceeds limit VLIM(X), switch is turned immediately OFF

3. VOUT falls (because no battery) , also VCH<Vpor (standard chargers full-rectified output). When VCH > Vpor and VOUT < VLIM(X) -> switch turned on again (also PWM is still HIGH) and VOUT again exceeds VLIM(X).

4. Software sets PWM = LOW -> CHAPS does not enter PWM mode

5. PWM low -> Startup mode, startup current flows until Vstart limit reached

6. VOUT exceeds limit Vstart, Istart is turned off

7. VCH falls below Vpor

Figure above: Battery removal during charging t t

Different PWM frequencies ( 2Hz and 32 Hz)

When a travel charger (2- wire charger) is used, the power switch is turned ON and OFF by the PWM input when the PWM rate is 2Hz. When the PWM is HIGH, the switch is ON and the output current lout = charger current - CHAPS supply current. When PWM is LOW, the switch is OFF and the output current lout = 0. To prevent the switching transients inducing noise in audio circuitry of the phone soft switching is used.

The performance travel charger (3- wire charger) is controlled with PWM at a frequency of 32Hz. When the PWM rate is 32Hz CHAPS keeps the power switch continuously in the ON state.

Baseband Module JP3

Technical Documentation

SWITCH

SWITCH

PWM (32Hz)

Figure 3. Switch control with 2Hz and 32 Hz frequencies (in this case 50% duty cycle)

Charger Current measurement

The charging current measurement is based on the reading of differential voltages over the shunt resistor at the CHAPS output lines. The voltage is measured and amplified by a differential amplifier and it is carried to the MCU A/D converter. Measurement area is up to 1400 mA and 1 A/D bit equals 1.85 mA. The charging current calibration is done with 0 mA and 500 mA in production test line. When charger is connected the current measurement connection is activated. The A/D-conversion result and charging current can be calculated from equations :

A/D readout = 1024 * VICHAR / VREF Charging current:

I=(V|char - V|CHAR(0mA)) * (500mA/(V|CHAR(500mA) - V|CHAR(0mA))

where VREF=2.82 V

VICHAR = voltage in ICHAR line

Technical Documentation Baseband Module JP3

Table 5. Charger current measurement

Name

Min

Typ

Max

Unit

Notes

VICHAR

0.46

0.69

0.92

V

Charging current is 0 mA. ( Calibration point )

163

250

334

A/D

1.22

1.44

1.65

V

Charging current is 500 mA. ( Calibration point )

443

522

598

A/D

1.98

2.19

2.39

V

Charging current is 1000 mA.

718

795

867

A/D

Figure 4. Charger current measurement

Battery identification

Different battery types are identified by a pull-down resistor inside the battery pack. The BSI line inside transceiver has a 22k pull-up to VA. The MCU can identify a battery by reading the BSI line DC-voltage level with a MCU (D201) A/D-converter.

Baseband Module JP3 Technical Documentation

Table 6. Battery Identification

Name

Min

Typ

Max

Unit

Notes

BSI

0

2.8

V

Battery size indication 22k pullup resistor to VA in phone

14.2

15

15.8

kohm

Indication of a BMS-2V vibra battery (900mAh NiMH)

9.5

10

10.5

kohm

Indication of a BMS-2S battery (900mAh NiMH)

37

39

41

kohm

Indication of a BLS-2 battery (900mAh Lilon)

48.5

51

53.5

kohm

Indication of a BLS-4 battery (1600mAh LiIon)

-5

5

%

Indication resistor and pullup resistor tolerance

BATTERY

BVOLT

BTEMP

BGND

2.8V

TRANSCEIVER

10n.

1

A/D BSI Conv.

MCU

1 *

Battery voltage measurement, VBATSW

Battery voltage can be measured up to 6.27 V from the VBATSW line. The absolute accuracy is low because of the voltage reference and A/D-converter +/- 8 LSB accuracy . This battery voltage measurement offset error must be calibrated with input voltage 4.1 V. The A/D conversion result can be calculated from equation:

A/D readout = 1024 * (VBAT* ( 0.45)) / VREF VREF=2.82 V For example:

4.1 V results 670 = 29Dh 3.6 V results 588 = 24Ch 3.0 V results 490 = 1EAh

Charger voltage measurement, VCHARG

Charger voltage can be measured up to 17.00 V from VCHARG line. The absolute accuracy is low because of the voltage reference and A/D-con-

Technical Documentation Baseband Module JP3

verter +/- 8 LSB accuracy. The A/D-conversion result can be calculated from equation :

A/D readout = 1024 * (VCHARG*(10/60.3)) / VREF VREF=2.82 V For example:

8.4 V results 506 = 1F9h

Battery temperature

The battery temperature is measured with a NTC inside the battery pack. The BTEMP line inside transceiver has a 100k pullup to VA. The MCU can calculate the battery temperature by reading the BTEMP line DC-voltage level with a MCU (D201) A/D-converter.

Table 7. Battery temperature

Pin

Name

Min

Typ

Max

Unit

Notes

3

BTEMP

0

2.90

V

Battery temperature indication 100k pullup resistor to VA in phone Battery package has NTC pull down resistor:

47k +/-5%@+25C , B=4050+/-3%

-1

1

%

100k pullup resistor tolerance

How Show Battery Temp Schematic

Battery temperature monitoring schematic diagram above

Based on 47kQ ± 5 % NTC with B = 4090 ±1.5 %. Without any alignment, with that and 1 % pull-up resistor, ± 2.5 °C accuracy is achieved between - 20 and +60 °C (± 3.5 °C @ -40 ... +85 °C).

Baseband Module JP3 Technical Documentation

Table 8. Battery temperature vs. AD readings and NTC resistance

T [C]

AD

R [ki>]

T m

AD

R [ki>]

t m

AD

R [ki>]

-40

963

1589

5

560

120.9

50

145

16.53

-35

942

1151

10

497

94.53

55

122

13.63

-30

915

842.8

15

436

74.40

60

103

11.30

-25

882

622.6

20

379

58.95

65

88

9.404

-20

842

464.1

25

327

47.00

70

74

7.865

-15

795

349.0

30

280

37.71

75

63

6.607

-10

743

264.6

35

238

30.43

80

54

5.573

-5

685

202.3

40

202

24.70

85

46

4.721

0

623

155.8

45

171

20.15

90

39

4.015

Vibra alerting device

A vibra alerting device is used for giving silent signal to the user of an incoming call. The device is not placed in the phone but it will be added to a special battery pack. The vibra is controlled with a PWM signal by the MCU via the BTEMP battery terminal.

Table 9. VIbra battery connection

Name

Min

Typ

Max

Unit

Notes

BTEMP

9

11

14

kHz

PWM control to VIBRA BATTERY

BSI

0

2.90

V

Battery size indication Phone has 100kohm pull up resistor.

14.2

15

15.8

kohm

Battery size indication resistor (vibra battery)

A 15kohm BSI resistor is needed to detect the vibra battery. It is only used to enable vibra selection in user menu. When alerting, VibraPWM signal is delivered to battery.

Technical Documentation

Baseband Module JP3

Supply voltage regulators and controlling

The heart of the power distribution is the PSA asic. It includes all the voltage regulators and feeds power to the whole system. The baseband digital and analog parts are powered from the VL and VA regulators which provide the 2.82 V baseband supply. The baseband regulators are active when the phone is powered on.

The PSA includes also two 2.82 V regulators (VRX and VTX) providing power to the RF section. These regulators can be controlled by the direct control signals from the MCU. The VRX regulator can also be controlled by the signal from the NASTA.

- VTX_ENA ( from MCU ) controls VTX regulator

- PSBS_ENA ( from NASTA ) controls VRX regulator In addition PSA includes also functions listed bellow:

- Buffer for the M2BUS.

The buffer translates the logical input signal to open-drain output.

Table 10. M2BUS buffer truth table

Input

Output

LOW

LOW

HIGH

Z

Baseband Module JP3 Technical Documentation

- Power on/off and reset logic. The Power off logic can be used as a watchdog.

- Supply voltage monitor and automatic reset/power-off.

VBATSW is internally divided and buffered battery voltage output. The A/D -converter input monitoring the battery voltage can be connected here. The circuit monitors the voltage at the VBAT input and forces the circuit to Reset if the voltage level is below allowed limit voltage, VBATcoff-. A hysteresis is included to prevent oscillation between different states.

- Battery charger detection.

Externally divided charger voltage VCHAR goes through PSA internal switch to VCHARSW output. The A/D -converter input monitoring the charger voltage can be connected here.

- Automatic on-chip current limiting

- On-chip thermal shutdown, which protects PSA from overheating. Thermal shutdown includes hysteresis in order to prevent oscillation during the thermal protection.

Table 11. Regulators VA and VL characteristic

Parameter Test Conditions

Min Typ Max

Unit

Output Voltage

VL, VA

2.73 2.82 2.90

V

Output current of the regulator (all regulators enabled)

IoutVL loutvA

0 40 0 100

mA mA

Quiescent current

VL: Iload = 0mA Iload = 40mA VA: Iload = 0mA Iload = 100mA

lq

200 220 200 220

^A ^A ^A ^A

Quiescent current Tamb = +25°C, VBAT=3.6V VL: Iload = 0mA Iload = 40mA VA: Iload = 0mA Iload = 100mA

lq

110 130 110 130

^A ^A ^A ^A

Quiescent current in Power-Off VL VA

Iqoff

6 15

^A ^A

Line regulation: VL, VA IoutVL = 40mA, IoutVL = 100mA, 3.25V < VBAT < 5.2V

^l^ VAline

20

mV

Load regulation: VL, VA

0mA <IloadVL< 40mA, 0mA < IloadVA < 100mA, 3.25V < VBAT < 5.2V

VAload

30

mV

Technical Documentation Baseband Module JP3

Table 11. Regulators VA and VL characteristic (continued)

Parameter Test Conditions

Min Typ Max

AC=0.5V square wave Slew rate = 50 mV/^s f = 500Hz ... 2kHz 3.5V <VBAT< 5.2V

VLlinetr VAlinetr

40

dB

Load transient: VL, VA

IloadVL 100^A to 40mA, IloadVA 100 ^A to 100mA in

10^s

3.25V <VBAT< 5.2V

AV Tree Note 1

40 20

^s

Current limit (VL,VA = 0 V) VL VA

'lim

60 180 150 450

mA mA

Power Supply Ripple Rejection 3.2V <VBAT< 5.2V 0mA < IloadVL < 40mA, 0mA < IloadVA < 100mA f = 10Hz ... 10kHz

PSRR

40

Cload=1[xF±20% load current 0mA

Note 2

160

^s

Note 1: Voltage deviation (AV) is the output voltage overshoot in transient response. Recovery time (Tree) is the time from the beginning of the transient response to the time point when the regulator output voltage first crosses the final stable value after overshoot.

Note 2: Settling time is defined from the time point of mode change Power-Off to Reset to the time when regulator output voltage is within 5% of the final value.

Table 12. Regulators VRX and VTX characteristic

Parameter

Symbol

Limits

Unit

Test Conditions

Min

Typ

Max

Output Voltage

VRX, VTX

2.73

2.82

2.90

V

Output currents of the regulators

loutvRX

0.05

50

mA

(all regulators enabled)

loutVTX

0.02

60

mA

Quiescent current

Iq

VRX: Iload = 0A

320

^A

Iload = 50mA

360

^A

VTX: Iload = 0A

320

^A

Iload = 60mA

360

^A

Baseband Module JP3 Technical Documentation

Table 12. Regulators VRX and VTX characteristic (continued)

Parameter Test Conditions

Min Typ Max

Iload = 60mA

Iq

180 195 180 195

^A ^A ^A ^A

Quiescent current in Power-Off VRX VTX

Iqoff

14 17

^A ^A

Line regulation: VRX, VTX loutVRX = 50mA, loutVTX = 60mA, 3.25V <VBAT< 5.2V

VRXline, VTXline

20

mV

Load regulation: VRX, VTX

50^A < IloadVRX < 50mA, 20^A < IloadVTX < 60mA, 3.25V <VBAT< 5.2V

VRXload, VTXload

30

mV

Line transient: VRX, VTX

AC=0.5Vpp square wave Slew rate = 50 mV/^s f = 500Hz 2kHz 3.5V <VBAT< 5.2V

VRXlinetr, VTXlinetr

40

dB

Load transient: VRX, VTX

IloadVRx 50^A to 50mA, IloadVTX 20^A to 60mA in 10^s 3.25V <VBAT< 5.2V

AV Tree

Note 1

40 20

^s

Current limit (VRX,VTX = 0 V) VRX VTX

Ilim

75 225 90 270

mA mA

Power supply ripple rejection 3.25V <VBAT< 5.2V 50^A < IloadVRX < 50mA, 20^A < IloadVTX < 60mA, f = 10Hz 10kHz f = 10Hz 50kHz f = 10Hz 100kHz

PSRRVRX,VTX

50 40 35

dB dB dB

Settling time,

Cload=1^F±20% load current 0mA

Note 2

100

^s

Note 1: Voltage deviation (AV) is the output voltage overshoot in transient response. Recovery time (Tree) is the time from the beginning of the transient response to the time point when the regulator output voltage first crosses the final stable value after overshoot.

Note 2: Settling time is defined from VTX_ENA/VRX_ENA rise to the time when regulator output voltage is within 5% of the final value.

Technical Documentation Baseband Module JP3

Operation modes

The circuit has three operational modes: Power-Off, Reset and PowerOn. The additional modes are the Protection mode and Battery disconnected (VBAT < VRth, master reset threshold). Respective conditions of the external signals are described in the NO TAG.

Table 13. Operational modes

MODE

PURX

VRX EN A

VTX EN A

VL VA

VRX

VTX

VBATSW

VCHAR -SW

PWRONBUFF

PowerOff

LOW

X

X

Z

Z

Z

Z

Z

LOW

Reset

LOW

L

L

2.8V

Z

Z

Z

Z

LOW

LOW

H

H

2.8V

2.8V

2.8V

Z

Z

LOW

PowerOn

HIGH

L

L

2.8V

Z

Z

VBATSW

VCHAR

XPWRONX

H

H

2.8V

2.8V

2.8V

VBATSW

VCHAR

XPWRONX

NOTE: VBATSW and VCHARSW are controlled by internal VSW_ENA-signal during power-on.

NOTE: PWRONBUFF is an inverted (and buffered) PWRONX. A logic LOW level at PWRONX (active LOW) will force a logic HIGH level at PWRONBUFF.

Power-Off Mode

In order to be in Power-Off mode VBAT must be above VRth.

During Power-Off mode PURX is at logical low level. VA, VL, VRX and VTX regulators are disabled and in high-Z low output state.

Entering Power-Off Mode

The PSA contains a watchdog counter that is reset by writing "1" - "0" sequence to input PWROFFX. "

The circuit goes to Power-off mode from Power-On after delay Toff if watchdog has not been reset during this time.

The other possibility to enter the Power-Off is from Reset, if the PSA can not enter Power-On mode because VBATcoff+ is not reached. This means that watchdog elapses before the microcontroller is able to produce a pulse to PWROFFX. If charger is present (VCHAR>VCHARth), transition from Reset to Power-Off can not occur but the circuit stays in Reset mode as long as battery has been charged above VBATcoff+.

The circuit goes to battery disconnected mode if battery voltage drops below master reset threshold (VRth-).

For testing purposes the watchdog can be disabled and reset by grounding the WD_DISX pin. In normal use it can be left floating (internal pull up).

Baseband Module JP3 Technical Documentation

Charging in Power-Off

Charging is not possible in Power-Off. Connecting a charger during Power-Off generates a rising edge on VCHAR input and the circuit enters Reset mode. Circuit stays in Reset as long as the battery is charged to the limit VBATcoff+.

If the watchdog elapses during Power-On when charger is connected, the circuit goes to Power-Off. Because charger detection is level sensitive, charger is detected and the circuit goes via Reset mode to PowerOn mode.

Reset Mode

The circuit goes into Reset mode from Power-Off when:

- the battery voltage is initiated (master reset) or

- logic low voltage in PWRONX is detected or

- charger voltage becomes available or

- when recovering from Protection mode

In Reset mode the VL and VA outputs are activated by an internal enable signal. The VRX and VTX have external enable inputs VRX_ENA and VTX_ENA. VBATSW and VCHARSW are disabled and PURX is LOW.

The circuit leaves the Reset mode after a delay Trd for Power-On if VBAT > VBATcoff+. Watchdog is reset when Power-On mode is entered.

The circuit goes into Reset mode from Power-On when the battery voltage VBAT drops below VBATcoff-.

VBAT is monitored internally, hence if voltage VBAT drops below the threshold (determined by internal resistors), transition from Power-on to Reset mode is done. If VBAT doesn't rise back above reset release limit in time Toff the Watchdog elapses and the circuit powers off.

To avoid PSA going to RESET mode due to fast transient, transition from Power-On to Reset mode is not done if VBAT is below VBATcoff- for shorter time than threshold detection delay Tdd.

The circuit leaves the Reset mode after a delay Trd if VBAT > VBATcoff+.

Technical Documentation Baseband Module JP3

Tdd Trr

Figure 6. Threshold detection delay Tdd and PURX reaction time Trr

Tdd Trr

Figure 6. Threshold detection delay Tdd and PURX reaction time Trr

Figure 7. Reset limits and hysteresis

Power-On Mode

In Power-on mode all the functions are active. VBATSW and VCHARSW outputs are activated by the internal enable signal VSW_ENA. PURX is high in Power-On.

From Power-On mode the circuit goes to Power-Off mode after a delay Toff (watchdog delay set by an external capacitor Cosc) if no writing sequence to PWROFFX from logical high level to low level has detected during this time.

In Power_on mode the circuit does not react on PWRONX pulse i.e. the circuit must be switched off by the system by not updating the watchdog writing in time Toff.

Baseband Module JP3

Technical Documentation

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