CTRLU Circuit

The Control block CTRLU controls all functions of the phone.

Block Description

CTRLU controls the watchdog timer in PSA. It sends a negative pulse at approximately 0,1 s to XPWROFF pin of the PSA to keep the power on. If CTRLU fails to deliver this pulse, the PSA will remove power from the system. When power off is requested CTRLU leaves PSA watchdog without reset. After the watchdog has elapsed PSA cuts off the supply voltages from the phone. CTRLU controls also the charger on/off switching in the PWRU block. Battery charging is controlled by CSW line, which is PWM-controlled output port.

Interface between microcontroller and the NASTA circuit is bidirectional 8-bit data bus with 4 address lines. Address, data and control lines are used in microcontroller as I/O-port pins. Data lines direction must be controlled with microcontroller data direction register. Interface includes address outputs NA0-3, data inputs (read) / outputs (write) ND0-7, chip select control output XNCS , read control output XNRD, write control output XNWR and interrupt input XINT. To minimize power consumption, control signals XRD and XCS should be in '0' state and address output NA0-3 and NWR in '1' state and data lines ND0-7 should be inputs .Buzzer is controlled by BUZZ_DRV PWM signal. Headset adapter is detected by HSCONN input.

- CTRLU - UIF and DISPLAY

Keyboard is connected directly to the controller. COL 0:3 are output lines and ROW 0:3 are input lines. Watchdog is updated same time with keyboard scanning (XPWROFF). Keyboard scanning is done by driving one COL to 0 V at time and ROWs are used to read which key is pressed.

Keyboards lights are controlled by KEYBLIGHT signal and LCD lights by LCDBLIGHT signal.

LCD controller interface to microcontroller is a bidirectional data line LCDDA, data serial clock line SCLK output, chip select control LCDENX output, command or display data control LCDDC output and reset control LCDRES output.

- CTRLU - RECEIVER

Received signal strength is measured over the RSSI line and intermediate frequency is measured over the IF line.

RX synthesizer and receiver are powered on/off by PSBS_EN line.

Technical Documentation Baseband Module JP3

- CTRLU - SYNTHESIZER

Frequency is controlled by the AFC signal. The synthesizer is controlled via the synchronous serial bus SDAT/SCLK. The data is latched to the synthesizer by the positive edge of the SLE line. The TX synthesizers power on/off is controlled by VTX_ENA signal.

- CTRLU - TRANSMITTER

The transmitter on/off state is detected over the TXI line. The TXE line activates the power module. The power is controlled via the TXC line which is a PWM-controlled output port (frequency about 9.4 kHz).

Extended standby mode for power saving

The extended standby mode is automatically activated when the phone is working in the control channel (FOCC). The NASTA runs this function, switching on/off the receiver's power supply.

PSPS_EN signal:

- The signal connects the RX regulator on via the PSA when it is in "1" state, in "0" state the RX regulator is off.

HPD_EN signal:

- The signal controls the RX synthesizers hardware power down function.

When it is in "1" state the RX synthesizer is powered up, in "0" state the RX synthesizer is powered down.

Main Components MCU

The H8/3093 is a CMOS microcontroller. All the memory needed 192kB ROM, 4kB RAM) except the EEPROM, is located in the controller. The MCU operating clock (2.4 MHz) is generated on the NASTA and the VCTCXO. The H8/3093 is operating in single-chip normal mode (mode 3) 192kbyte address space, so all input/output pins are used as I/O-ports.

Pin Number

Port

Signal

Description

1

PB0

SDAT

Synthesizer data line

2

PB1

RSSI_READY

RSSI readings synchronization

3

PB2

VIBRA_CONTROL

Vibra alerting device on/off

4

PB3

RXD

M2BUS net free timer input

5

PB4

EAREN

Earphone amplifier enable

6

PB5

XPWROFF

Power off control

7

PB6

PWRON

Power button state

8

PB7

SLE

Synthesizer latch enable

9

P90

TXD

Serial interface (M2BUS)

Baseband Module JP3 Technical Documentation

Pin Number

Port

Signal

Description

10

P92

RXD

Serial interface (M2BUS)

11

P94

ECLK

Serial data clock for EEPROM

12

VSS

GND

13 - 20

P30 - P37

ND0 - ND7

Parallel data bus for NASTA

21

VCC

VL

22

P10

NA0

Address line for NASTA

23

P11

NA1

Address line for NASTA

24

P12

NA2

Address line for NASTA

25

P13

NA3

Address line for NASTA

26

P14

XNCS

NASTA chip select

27

P15

XNWR

Write control to NASTA

28

P16

XNRD

Read control to NASTA

29

P17

LIGHTS

Keypad backlight control

30

VSS

GND

31 - 34

P20 - P23

C0L0-C0L3

Keypad outputs

35 - 38

P24 - P27

R0W0 - R0W3

Keypad inputs (Input pullup used)

39

P50

SCLK

Serial data clock for lcd driver

40

P51

LCDENX

Chip select signal for lcd driver

41

P52

LCDDC

Display or Command data

42

P53

LCDSDA

Data line for lcd driver

43

P60

VTX_ENA

TX synthesizer enable. Active high

44 - 45

MD0 - MD1

Mode selection

46

NC

NC

47

STBY

VL

48

RES

XRES

Reset from PSA

49

NMI

NC

50

VSS

GND

51

EXTAL

CLKMCU

External system clock from NASTA

52

XTAL

NC

53

VCC

VL

54

P63

TXE

Transmitter on/off

55

P64

LIM

Battery cut off limit selection

Technical Documentation Baseband Module JP3

Pin Number

Port

Signal

Description

56

P65

XEAR_EN

Headset earpiece amplifier control

57

RESO

NC

58

AVSS

GND

59

P70

VBATSW

Battery voltage

60

P71

VCHARG

Charger voltage

61

P72

ICHAR

Charging current measurement

62

P73

BTEMP

Battery temperature

63

P74

RSSI

Received signal strength

64

P75

TXI

Transmitter state monitor

65

P76

HSCON

Headset detecting voltage

66

P77

BSI

Battery size indicator

67

VREF

VA

68

AVCC

VA

69

P80

XINT

Interrupt request from NASTA

70

P81

LCDRES

LCD reset signal

71

P82

LCDBLIGHT

LCD backlight control

72

P83

HEADSW

Headset switch indicator

73

PA0

MIC_EN

Internal microphone control

74

PA1

LCDCLK

LCD clock from NASTA

75

PA2

BUZZ_DRV

PWM output for buzzer

76

PA3

SCLK

Serial clock for synthesizer

77

PA4

CSW

Charging control PWM

78

PA5

EDATA

Eeprom data line

79

PA6

TXC

Transmitter power control

80

PA7

XMIC_EN

Headset microphone control

Baseband Module JP3

Technical Documentation

EEPROM

There is one 4kbyte EEPROM with 32byte OTP memory in the phone. The EEPROM is a nonvolatile memory in which the tuning data for the phone is stored. In addition, it contains the short code memory locations to retain user selectable phone numbers. The OTP memory is ROM area for identification and security purposes.

Table 1. EEPROM signals:

Pin No

Signal

Description

5

SDA

I2C bus data

6

SCL

I2C bus clock

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