Technical Documentation System Module

Signal name

From

To

Parameter

Minimum

Typical

Maximum

Unit

Function

SENA1

MAD

PLL

Logic high "1"

2.78

3.08

3.38

V

Dual PLL enable

Logic low "0"

0

0.1

0.2

V

Current

50

uA

Load capacitance

10

pF

SDATA

MAD

PLL

Logic high "1"

2.78

3.08

3.38

V

Synthesizer data

Logic low "0"

0

0.1

0.2

V

Load impedance

10

kohm

Load capacitance

10

pF

Data rate frequency

3.25

MHz

SCLK

MAD

PLL

Logic high "1"

2.78

3.08

3.38

V

Synthesizer clock

Logic low "0"

0

0.1

0.2

V

Load impedance

10

kohm

Load capacitance

10

pF

Data rate frequency

3.25

MHz

AFC

RFI2

VCTCXO

Voltage

0.26

3.94

V

Automatic frequency control signal for VCTCXO

Resolution

11

bits

Load impedance (dynamic)

10

kohm

Noise voltage

500

uVrms

10...10000Hz

Settling time

1

ms

RFC

VCTCXO

MAD

Frequency

13

MHz

High stability clock signal for logic circuits

Signal amplitude

0.2

Vpp

Load resistance

10

kohm

Load capacitance

5

pF

RFCGND

VCTCXO

MAD

RFC signal ground, not used

RXIP/RXIN

CRFRT

RFI2

Output level

25

570

mVpp

Differential RX 13 MHz signal to baseband

Source impedance

300

ohm

Load resistance

10

kohm

Load capacitance

5

pF

Phase imbalance

2

deg

Amplitude imbalance

1

dB

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