Synthesizer control timing diagrams

RXPWR

SYNTHPWR.

SENA1

SDATA/ SCLK

2us min

50 us

#bits

IF R 22

IF N 22

RF R 22

RF N 22

time slots

RX 0

RX 0

SYNTHPWR RXPWR

TXPWR

SENA1

SDATA/ SCLK

Jill.

System Module

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