Digital control

The baseband functions are controlled by the MAD asic, which consists of a MCU, a system ASIC and a DSP. The DCS/PCN specific asic is named as MAD2. There are separate controller asics in TDMA and JDC named as MAD1 and MAD3. All the MAD asics contain the same core processors and similar building blocks, but differ from each other in system specific functions, pinout and package types.

MAD2 contains following building blocks:

- ARM RISC processor with both 16-bit instruction set (THUMB mode) and 32-bit instruction set (ARM mode)

- TMS320C542 DSP core with peripherals:

- API (Arm Port Interface memory) for MCU-DSP communication, DSP code download, MCU interrupt handling vectors (in DSP RAM) and DSP booting

- Serial port (connection to PCM)

- Timer

- DSP memory

- BUSC (BusController for controlling accesses from ARM to API, System Logic and MCU external memories, both 8- and 16-bit memories)

- System Logic

- CTSI (Clock, Timing, Sleep and Interrupt control)

- MCUIF (Interface to ARM via BusC). Contains MCU BootROM

- DSPIF (Interface to DSP)

- MFI (Interface to COBBA AD/DA Converters)

- CODER (Block encoding/decoding and A51&A52 ciphering)

- AccIF(Accessory Interface)

- SCU (Synthesizer Control Unit for controlling 2 separate synthesizer)

- UIF (Keyboard interface, serial control interface for COBBA PCM Codec, LCD Driver and CCONT)

- SIMI (SimCard interface with enhanched features)

- PUP (Parallel IO, USART and PWM control unit for vibra and buzzer)

System Module

Technical Documentation

The MAD operates from a 13 MHz system clock, which is generated from the 13Mhz VCXO frequency. The MAD supplies a 6,5MHz or a 13MHz internal clock for the MCU and system logic blocks and a 13MHz clock for the DSP, where it is multiplied to 52 MHz DSP clock. The system clock can be stopped for a system sleep mode by disabling the VCXO supply power from the CCONT regulator output. The CCONT provides a 32kHz sleep clock for internal use and to the MAD, which is used for the sleep mode timing. The sleep clock is active when there is a battery voltage available i.e. always when the battery is connected.

The MCU program code resides in an external program memory. MCU work (data) memory size is 512kbits. A serial EEPROM is used for storing the system and tuning parameters, user settings and selections, a scratch pad and a short code memory. The EEPROM size is 64kbits. The memory variation is managed using memory components with the same packages and pinouts for all memory sizes of the given types. The system parameters contain information of the used memories in that end product. The selected memory packages are TSOP48 for ROM, STSOP32 for RAM and SO8S for EEPROM .

The used flash memories are capable to perform erase and write operations with the supplied 3V programming voltage.

The BusController (BUSC) section in the MAD decodes the chip select signals for the external memory devices and the system logic. BUSC controls internal and external bus drivers and multiplexers connected to the MCU data bus. The MCU address space is divided into access areas with separate chip select signals. BUSC supports a programmable number of wait states for each memory range.

The MCU program code resides in the program memory. The program memory size is 8Mbits (512kx16) The default package is TSOP48.

The power down pin of FLASH is utilized in the system sleep mode by connecting the VCXOPwr to the flash power down pin to minimize the flash power consumption during the sleep.

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