R308 Resistor Nokia

tAVAV tAVQV tELQV tGLQV

Read Cycle Time

Address to output delay CE# low to output delay

OE# low to output delay

Min. 85ns Max. 85ns Max. 85ns Max. 35ns

Figure 19: Intel Synchronous Four-Word Burst Read

Figure 19: Intel Synchronous Four-Word Burst Read

Nokia 3510 Coil

Synchronous Four-Word Burst Read Intel AMD

R2 tAVQV

R304 tCHQV

R305 tCHQX

R307 tCHTL/H

R308 tELTL

Address to output delay CLK to output delay

Output hold from CLK

CLK to WAIT asserted

CE# low to WAIT active

Max. 85ns Max. 14ns Min. 5ns Max. 14ns Max. 14ns

Figure 20: Intel Write

Figure 20: Intel Write

Anatomical Position Chart

Write

Intel AMD

W1 tPHWL

W2 tELWL

W4 tDVWH

W5 tAVWH

W10 tVPWH

W18 tVHWH AMD

Reset# High recovery to WE# low Min 150ns

CE# Setup to WE # low Data setup to WE# High Address setup to WE# High Vpp setup to WE# high

ADV# setup to WE# high

Min. 0ns Min. 60ns Min. 60ns Min. 200ns Min. 70ns

Some of the more important timing specifications for the AMD flash are:

Figure 21: AMD Asynchronous Read

Figure 21: AMD Asynchronous Read

avd# Asynchronous Read tOE Output enable to output valid tCE Access time from CE#-low tACC Asynchronous Access time

Max. 35ns Max. 90ns Max. 90ns

Figure 22: AMD Synchronous Burst Read

Figure 22: AMD Synchronous Burst Read

Synchronous Read tACC Initial Access Time tAVDS

AVD# setup time to CLK

Max. 100ns Min. 5ns tACS Address setup time to CLK toE Output enable to output valid tcEs CE# setup time to CLK

Min. 5ns Max. 35ns Min. 5ns

AMD Write

AMD Write

Write

Write Cycle Time tcs CE#-low setup time

Write Pulse Width

Notes:

Min. 100ns Min. 0ns Min. 60ns

1.DIn is Data input to the device.

2.DQ7# is the output of the complement of the data written to the device.

3.Dout is the output of the data written to the device.

Flash Programming

Connections to Baseband

The flash programming box, FPS8, is connected to the baseband using a galvanic connector or test pads for galvanic connection. The UEM watchdog is disabled during flash programming to prevent a hardware reset of the timer. The flash programming interface connects the flash prommer to the UPP via the UEM and the connections correspond to a logic level of 2.7 V. The flash prommer is connected to the UEM via the MBUS (bi-directional line), FBUS_TX, and FBUS_RX all located on the ACCDIF[2:0]. The programming interface connections between the UEM and the UPP constitute the MBUS_TX, MBUS_RX, FBUS_TX, and FBUS_RX lines, all located on the IACCDIF[5:0]. The interface also uses the BSI (Battery_Size_Indicator) and the PURX signal connections for the con nections between the UEM and the UPP. Baseband Power Up

The baseband power is controlled by the programming jig in production, and the flash prommer (via the flashing battery) in reprogramming situations. Reprogramming uses the flashing battery to apply a supply voltage to the battery terminals and power up the baseband. The battery and supply voltage generated by the flash prommer interface equipment should not exceed 4.2 V.

Flash Programming Indication

Flash programming is indicated to the UPP using the MBUS_RX signal between UPP and UEM. The flash prommer keeps the MBUS line low during UPP boot to indicate that the flash prommer is connected and flag reprogramming condition to disable the UEM watchdog. If the UPP MBUS_RX signal is low the MCU enters flash programming mode. In order to avoid accidental entry to the flash programming mode, the MCU only waits for a specified time to get input data from the flash prommer. If the timer expires without any data being received, the MCU will continue the boot sequence. The MBUS signal from the UEM to the flash prommer is used as a clock for the synchronous communication and the MBUS_RX signal supplies the flash programming clock to the UPP. During flashing, the phone cannot be booted using conventional power down and power up on the battery line.

The flash prommer indicates the flash programming to the UEM by writing an 8-bit password to the UEM. The data is transmitted on the FBUS_RX line and the UEM clocks the data into a shift register. When the 8-bits have been shifted in the register, the flash prommer generates a falling edge on the BSI line. This loads the shift register contents in the UEM into a compare register. If the contents of the compare register match the default value preset in the UEM, the flash prommer will again pull the MBUS signal to the UEM low in order to indicate to the MCU that the flash prommer is connected. The UEM reset state machine performs a reset to the system by keeping PURX low for 10-100 ms. The UEM flash programming mode is valid until the MCU sets a bit in the UEM register that indicates the end of the flash programming. Setting this bit also clears the compare register in the UEM previously loaded at the falling edge of the BSI signal. Setting this bit also enables and resets the UEM watchdog timer to its default value and causes the UEM to generate a reset to the UPP.

In order to avoid spurious loading of the compare register, the BSI signal is gated during the UEM master reset and when PURX is low. The BSI signal should not change state in normal operation unless the battery is removed in which case the BSI signal will be pulled high.

When the MCU boots it looks for flash programming indication on the MBUS_RX signal. If this signal is pulled low the MCU sets up the UART (Universal Asynchronous Receive-Transfer) module in synchronous mode and uses the FBUS_TX signal to indicate to the

MCU Boot flash prommer that it is ready to accept the secondary download code. All flash programming software is downloaded to the UPP internal MCU SRAM.

The MCU also ends up in flash programming mode if the flash is empty, indicated by FFH in the first memory location in the flash.

Flash Identifiers

The flash has a manufacturer and device identifier for electrical identification. This information is used by the flash programming equipment to create the flash identifier for identifying which device is mounted on the board and correctly setup the EEPROM emulation.

The flash identifier indicates to the MCU, the hardware environment it is working in, in terms of the number of flashes as well the type, block-size, and configuration of each. The flash identifier is necessary because DCT4 supports many different flash manufacturers. The flash identifier consists of five words as described below:

The flash identifier is stored in the MCU code space. The MCU code space in the memory starts at either 80000H or 100000H depending upon the size of the MCU software.

This word contains information about the number of flash devices connected to the UPP. It is possible to setup the UPP to support two devices. The MSB indicates the number of flashes used by the baseband. The number of WAIT states for the random access is specified over the next 3 bits in this word. The number of WAIT states is specified relative to the system clock used. The MCU PLL factor (specifying the MCU CLK frequency as a multiple of system CLK) is specified in the next 2 bits and whether the flash has Read-While-Write (RWW) capabilities is specified on the LSB.

Second Word

This work contains information about flash sectors available for EEPROM emulation. If no RWW capability is indicated in the first word, this field then contains information about the serial EEPROM that is used in the system. The flashes used in NHM-8NX all have RWW capability.

This word contains similar information as the first word, but the information is about the second flash if such is used.

Fourth Word

This word contains information about the sector configuration of the second flash.

First Word

Third Word

Fifth Word

This word contains information regarding the external SRAM if one is used for the baseband. The information specifies the size of the SRAM and the number of WAIT states to be used when accessing it. External SRAM is not supported by NHM-8NX.

EMC Strategy

The NHM-8NX phone complies with the given CE and SPR requirements concerning EMC and ESD. Attention has been paid to obtaining immunity in the PWB layout itself, and the implementation of filters in the circuit design.

Requirements for EMC and ESD:

CE requirements for EMC and ESD according to ETS 300 342-1

Internal requirements for EMC and ESD are according to SPR4

PWB strategy

PWB construction

The pwb in NHM-8NX is a 6-layer board with RCCu-foil, 17u cu and FR4 dielectric. Via types are through hole, laser via and buried via. The pwb layers has been defined to be: Layer 1: Component placement Layer 2: BB+RF Layer 3: RF Layer 4: Ground Layer 5: BB+RF Layer 6: Ground

PWB immunity

The pwb has been designed to shield all tracks from the bottom connector and all lines susceptible for radiation. Sensitive PWB tracks have been drawn with respect to shielding by having groundplane over and under the tracks, and ground close to the tracks at the same layer.

The edge of the pwb has been designed to control the direction of the ESD pulse by implementing a low impedance path for ESD. This is done by an open gold layer of 0,7mm at both sides of the pwb.

Keyboard

The keyboard PWB layout consists of a grounded outer ring and either a "trefoil pattern" grid (matrix) or an inner pad. This construction makes the keys immune for ESD, as the keydome will have a low ohmic contact with the PWB ground.

Power ON Key

The power ON key interface on UEM (PWRONX) is protected via RC filtering and controlled PWB layout.

PWB lines and filters concerning immunity

Audio lines

In order to obtain good signal to noise ratio and good EMC/ESD immunity the audio lines has been carefully routed with respect to obtaining low impedance in the signal path and obtain a proper shielding.

Microphone lines

Microphone signals are input lines and therefore very sensitive to radiated fields. Immunity for radiated fields is done by routing the microphone lines in shielded layer 5 and in parallel for obtaining a low impedance path and with respect to a common noise point of view in the signal path. This is applied for both internal and external microphone lines. Microphone lines from the bottom connector are routed on layer 2 to the filters and at layer 5 from filters to the UEM IC.

The ESD/EMC protection circuits are C101, C102, C103 and Z100 for Internal microphone and Z101 for external microphone.

EAR lines

EAR lines are output signals, also routed on shielded layer 5, to obtain immunity for conducted emission towards UEM. Internal EAR lines are EMC/ESD protected by radiated fields from the earpiece by Z150 and further suppressed by the low impedance signal path in the pwb.

The same pwb outline has been implemented for the SALT speaker. Low ohm coils L180/L181 are used in series with the speaker for immunity against incoming fields from the speaker.

Charger lines

Ground from charger is connected directly to common PWB ground for low impedance path to the battery.

The positive charger line is ESD, EMC and short circuit protected by the circuit: F100, L100,C100 and V100. The routing is in shielded layer 5 to provide immunity to this line when in pulse charge mode and to obtain immunity from UEM IC.

This line is EMC/ESD protected by routing on shielded layer 5 and by placement of resistor R155 close to the bottom connector.

Prod Test Points

Production test points TP2, TP3 and TP7 have 100ohm resistors, implemented in signal lines to limit bandwidth and improve EMC and ESD performance. These resistors are part of quad pack R108. Additionally spark gaps are added to improve the ESD robustness.

Battery Supply filtering

Battery supply lines to the UEM IC are filtered with two LC filters Z261,Z264,C261 and C264. These filters provide immunity against conducted RF noise.

SIM interface

The SIM interface has several levels of protection. All active line are protected/filtered via SIM ASIP (R386) (Application Specific Integrated Passive, part with RC-filter and Diodes integrated) and 10pF. The 10pF have shown to reduce 2nd harmonic spurious in GSM1800 band. Additionally sparkgap has been added on pin 5 for preventing ESD pulses to jump to UPP.

DC-Out interface

The DC-Out interface is protection with tranzorber diodes (V318) on both "power" and "CTI" pads.

LCD metal frame

The LCD metal frame is connected to the PWB ground, via springs in all four corners. Bottom connector

The immunity strategy concerning the bottom connector lines is by shielding all lines to this part in order to prevent radiation in the phone itself when external accessory is connected and to prevent radiated fields disturbing the lines as well. Appropriate discrete filters close to the bottom connector are implemented for EMC and ESD protection.

Headint

Mechanical shielding

NHM-8NX has metal shield over RF parts and BB parts to provide immunity for internal radiation and immunity for external fields. SIM card connector is placed below the battery to provide maximum immunity, to the SIM card, against RF fields from the antenna.

Security

The phone flash program and IMEI code are software protected, using an external security device that is connected between the phone and a PC. The security device uses IMEI number (IMEI is stored in UEM non-volatile memory cells), the software version number and a 24bit hardware random serial number that is read from the UPP, and calculates a flash authority identification number, that is stored into the phone (emulated) EEPROM. For further information see ].

Test Interfaces

Through MBUS or FBUS connections, the phone HW can be tested by PC software (Phoenix) and production equipment (FLALI/FINUI/LABEL).

Production / After Sales Interface

Test pads are placed on engine PWB, for service and production purposes, same test pattern is used for after sales purposes as well:

Figure 23: Production/Test/After sales interface

Figure 23: Production/Test/After sales interface

R308 Resistor Nok
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Responses

  • marilena
    Where is r308 resistor in mobile?
    6 years ago

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