N301 performs the required power on timing. The PSCLD, N301 internal power on and reset timing is defined by the external capacitor C330. This capacitor determines the internal reset delay, which is applied when the PSCLD, N301 is initially powered by applying the battery. The baseband power on delay is determined by C311. With a value of 10 nF the power on delay after a power on request has been active is in the range of 50-150 ms. C310 determines the PSCLD, N301 internal oscillator frequency and the minimum power off time when power is switched off.
The sleep control signal from the ASIC, D151 is connected via PSCLD, N301. During normal operation the baseband sleep function is controlled by the ASIC, D151 but since the ASIC is not power up during the startup phase the sleep signal is controlled by PSCLD, N301 as long as the PURX signal is active. This arrangement ensures that the 13 MHz clock provided from RF to the ASIC, D151 is started and stable before the PURX signal is released and the baseband exits reset. When PURX is inactive, high, sleep control signal is controlled by the ASIC D151.
N301 requires capacitors on the input power supply as well as on the output from each regulator to keep each regulator stable during different load and temperature conditions. C305 and C335 are the input filtering capacitors. Due to EMC precautions a filter using C337, L310, C335, L311, C338 and C339 has been inserted into the supply rail. This filter reduces the high frequency components present at the battery supply from exiting the baseband into the battery pack. The regulator outputs also have filter capacitors for power supply filtering
Technical Documentation System Module and regulator stability. A set of different capacitors are used to achieve a high bandwith in the suppression filter.
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