The external microphone audio signal is applied to the baseband system connector and connected to the audio block using signals XMIC and SGND. In order to improve the external audio performance the input circuitry is arranged in a sort of dual ended. A wheatstone type of bridge configuration is created by resistors R216, R217, R219 and R220. The signal is attenuated around 20 dB to not cause distortion in the microphone amplifier. The microphone signal is attenuated by resistors R216, R207 and R217. Two allow the external earpiece to be driven dual ended the external microphone signal ground is connected to the negative output of the external audio earpiece amplifier. This means that with reference to audio codec, N200 ground there is a signal level on the SGND line. This arrangement requires that the external microphone amplifier supplies the signal on the SGND line to the XMIC line. With this arrangement the differential voltage over R207 caused by the signal in the SGND line is canceled. There is however a common mode component which is relatively high presented at both the external microphone input pins at the audio codec input, pins 22 and 23. The microphone amplifier has a good common mode rejection ratio but a slight phase shift in the signals will remove the balance. To compensate
System Module Technical Documentation for this the signal from the external earpiece amplifier positive output, which also feeds the external audio output from the baseband is feed to the remaining resistors in the bridge, R219 and R220. This arrangement will attenuate the common mode signal presented to the microphone amplifier caused by the audio signal in the SGND line. Since the positive output from the audio codec, XEAR signal introduces a DC signal to the microphone amplifier the DC signal on the XMIC and SGND lines are blocked by capacitors C218 and C220.
The external audio output is the XEAR signal on the system connector pin. The XEAR signal is taken from audio codec N200 pin 6. The output impedance is increased to 32 ohms by resistors R222 and R214. This resistors prevents the output amplifier from being short circuited even if the pin at the system connector is short circuited. An ESD capacitor, C225, is connected to ground at the connection point of R222 and R214. R222 is added to N200 pin 6 output as the output amplifier can not be loaded directly with the ESD capacitor. The DC voltage at the XEAR output is used to control the mute function of the accessory. When internal audio is selected the XEAR amplifier in N200 is switched off and the DC voltage at the output on pin 5 is removed. External audio output level is adjusted by the variable gain amplifier in the N200 by MCU via the serial control bus from the ASIC, D151. L206 and C 214 is EMC protection for the XEAR signal at the system connector. This filter also prevents RF signals induced in the external cables from creating interference in the audio codec output stage.
The DSP used in NHE-5 is the TI 320C541. This is a 16 bit DSP that can use external and/or internal memory access. The DSP can operate in two modes microprocessor mode or microcontroller mode. The difference between the two modes are that in microprocessor mode the DSP boots from external memory while in the microcontroller mode the DSP boots from internal ROM. The DSP external memory access is devided into data, program and I/O access. The type of access is indicated on three control pins that can be used for memory control.
The DSP, D152 executes code from the internal ROM. The baseband also provides external memories for the DSP, D410, D411. The DSP is capable of addressing 64 kword of memory. The memory area is divided into a code execution area and a data storage area. The code execution area is located at address 8000H-FFFFH in the internal ROM. The external memories are arranged in such a way that the DSP can access the external memories both as data storage and code execution. The memory chip select is taken from the memory access strobe signal from the DSP. This means that the memory is active during any memory access. The SRAMs are configured in chip select controlled write mode. This means that both the write signal and the output enable signal are active at the same time, and the actual write occours at the rising edge of the chip select signal. This implementation is required since the DSP supports only one signal for write/read control.The DSP, D152 executes code from the internal ROM. The baseband also provides external memories for the DSP, D410, D411. The DSP is capable of addressing 64 kword of memory. The memory area is divided into a code execution area and a data storage area. The code execution area is located at address 8000H-FFFFH in the internal ROM. The external memories are arranged in such a way that the DSP can access the external memories both as data storage and code execution. The memory chip select is taken from the memory access strobe signal from the DSP. This means that the memory is active during any memory access. The memories are connected in such a way that the write control is CE controlled write. This means that both the write signal and the output enable signal are active at the same time. This implementation is required since the DSP supports only one signal for write/read control.
The DSP is operating from the 13 MHz clock. In order to get the required performance the frequency is internally increased by a PLL by a factor of 3. The PLL requires a settling time of 50 us after that the clock has been supplied before proper operation is established. This settling counter is inside the DSP although the ASIC, D151 contains a counter that will delay the interrupt with a programmable amount of clock cycles before the interrupt causing the clock to be switched on is presented to the DSP. The DSP has full control over the clock supplied to it. When the DSP is to enter the sleep mode the clock is switched off by setting a bit in the ASIC register. The clock is automatically switched on when an interrupt is generated.
The DSP also has two synchronous serial channels for communication. One channel is used for data transmission between the DSP and the audio codec. This channel is operating at 512 kbits and clock and synchronization signal is provided by the ASIC, D151. The other channel is used for debugging purposes and uses the same clock and synchronization signals. The DSP has an interrupt controller servicing four interrupts and one non maskable interrupt, NMI. The interrupts have fixed priority which can only be changed by changing the interconnection between the interrupt sources by HW.
The ASIC contains DSP support functions as modulator,encryption/decryption using algorithms A5/A51, RF power ramp generation/AGC control, AFC control, Synthesiser serial interface, frame counters, timer, RFI2 interface, RX and TX
Technical Documentation power control timing. RF power ramp timing/AGC control, AFC control, synthesiser control are timed to the value of the frame counter. This means that data is loaded into the registers and transferred when the frame counter and the reference value matches. This allows timing of synthesiser control power ramp and start of TX data to be controlled very precisely.
As the receiver and the transmitter is not operating at the same time the TX power ramp function is used to control the AGC in the receiver during the reception. This requires the DSP to continously modify the values in the TX ramp SRAM to fit the ramp during TX and the AGC value during reception.
The DSP is accessing the ASIC in the DSP I/O area. 2 wait states are required for the ASIC access. Some of the DSP registers located in the ASIC are retimed to the internal ASIC clock and requires special handling with respect to consecutive writing. This means that the same register can not be written again until a specified time has passed. To cope with this DSP is inserting NOP instructions to satisfy this requirement.
The DSP supports 4 external interrupts. Three interrupts are used. The ASIC, D151 generates two of the interrupts. One interrupt is generated by RFI2, N450 auxiliary A/D converter. This interrupt is generated when a baseband measurement a/d conversion is completed. The interrupts to the DSP are active low.
INT0 which is the highest priority interrupt is used for data reception from the receiver and is generated by the ASIC. INT1 signal is used for auxiliary A/D channel conversions generated by the RFI2. This interrupt is generated by RFI2 and is a result of measurement requests from the DSP. There are 8 auxiliary channels supported by the RFI2, not all are used in HD842 even if most of the channels are connected. INT3 is a low priority interrupt generated by the ASIC timer. The DSP programs the timer value and an interrupt is given when the timer expires. The interrupt must be active at least 1 ??? DSP clock cycle as it is sampled on the rising/falling edge by the DSP. All interrupts are active
INT0 is used for the reveiver A/D converter in RFI2. The ASIC reads the data from the receiver path A/D converter in RFI2 at every data available signal activation from the RFI2. After the data transfer when the data is stored in the ASIC the ASIC generates a receiver interrupt to the DSP using INT1 signal. The DSP enters the interrupt routine and services the interrupt and reads the data from the ASIC.
INT1 signal is used for the auxiliary A/D converter channels in RFI2. These A/D channles are used for baseband battery voltage monitoring. Two channels are used for battery monitoring. The start of the A/D conversion task is timed in such a way that auxiliary channel 1 results are measured during transmission whne the Pa is active and channel 8 is measuring when the PA is off.
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